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Silicon Software
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Silicon Software produces off-the-shelf and customized OEM hardware
and software solutions offering a comprehensive portfolio of frame
grabbers for Machine Vision - six digital interface standards, internal
and external image acquisition and image processing devices.
Silicon Software framegrabbers feature FPGA's for accelerated image
processing for industrial automation, robotics and machine vision.
They have been a globally-recognized technology leader since 1990
in the development of image processing boards and software tools
to ease FPGA programming.
Silicon Software's award-winning VisualApplets software enables
graphic programming of their FPGA vision processors using a flowchart
type GUI that allows vision application engineers and software programmers
to implement demanding, real time and time-sensitive applications
on FPGA hardware within minutes.
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Models |
On-board
memory |
Standard |
Configuration |
I/O
module interface |
Power
output |
A-Series:
Image acquisition frame grabbers for Area and Line scan cameras.
Non-programmable. |
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microEnable
5 ironman AD8-PoCL |
1 GByte |
Camera Link 2.0 |
CL-full, CL-deca |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
microEnable
5 ironman AQ8-CXP6D |
1 GByte |
CoaXPress 1.0/1.1 |
CXP-1, -2, -3, -5, -6; 4 cameras |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
Power over CXP; SafePower |
microEnable
5 marathon ACL |
512 MByte |
Camera Link 2.0 |
CL: -base, -dual, -medium, -full, -deca |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
microEnable
5 marathon ACX-QP |
1024 MByte |
CoaXPress 1.0/1.1 |
CXP-1, -2, -3, -5, -6; 4 cameras |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
Power over CXP; SafePower |
microEnable
5 marathon AF2 |
512 MByte |
Camera Link HS |
Dual CLHS F2 |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable
IV AD1-CL |
128 MByte |
Camera Link 2.0 |
CL-lite, -base, -dual, -medium |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable
IV AD1-mPoCL |
128 MByte |
Camera Link 2.0 |
CL-base, CL-dual base, CL-medium |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
microEnable
IV AD1-PoCL |
128 MByte |
Camera Link 2.0 |
CL-lite, -base, -dual, -medium |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
microEnable
IV AD4-CL |
256 MByte |
Camera Link 2.0 |
CL-base, -dual, -medium, -full, -deca, non-standard formats |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable
IV AD4-CL (LVTTL) |
256 MByte |
Camera Link 2.0 |
CL-base, -dual, -medium, -full, -deca, non-standard formats |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable IV AD4-LVDS |
256 MByte |
LVDS |
Dual-LVDS |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable IV AD4-PoCL |
256 MByte |
Camera Link 2.0 |
CL-base, CL-dual base, CL-medium |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
microEnable
IV AD4-PoCL (LVTTL) |
256 MByte |
Camera Link 2.0 |
CL-base, -dual, -medium, -full, -deca, non-standard formats |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
microEnable
IV AQ4-GE |
256 MByte |
GigE Vision |
Single Link, LAG (specific protocol) |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable
IV AQ4-GPoE |
256 MByte |
GigE Vision |
Single Link, LAG (specific protocol) |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
Power over Ethernet, PC power separate |
microEnable
IV AS1-PoCL |
128 MByte |
Camera Link 2.0 |
CL-lite, CL-base |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
Models |
On-board
memory |
Standard |
Configuration |
I/O
module interface |
Power
output |
V-Series:
FPGA Programmable Image processing frame grabbers for Area and Line
scan cameras. |
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LightBridge
VCL (Pre-Production) |
2 GByte |
Camera Link 2.0 |
CL-base, -dual, -medium, -full, -deca |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
microEnable
5 ironman VD8-PoCL |
1 GByte |
Camera Link 2.0 |
CL-full, -deca, and non-standard formats |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
microEnable
5 ironman VQ8-CXP6D |
1 GByte |
CoaXPress 1.0/1.1 |
CXP-1, -2, -3, -5, -6; up to 4 cameras |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
Power over CXP, |
microEnable
5 marathon VCL
|
2 GByte |
Camera Link 2.0 |
CL-base, -dual, -medium, -full, -deca |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
microEnable
5 marathon VF2 |
2 GByte |
Camera Link HS |
Dual CLHS F2
|
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable
IV VD1-CL |
256 MByte |
Camera Link 2.0 |
CL-base, -dual, -medium, -full, -deca |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable
IV VD4-CL |
512 MByte
|
Camera Link 2.0 |
CL-base, -dual , -medium, -full, -deca including non-Standard formats
|
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable
IV VD4-CL (LVTTL)
|
512 MByte
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Camera Link 2.0 |
CL-base, -dual , -medium, -full, -deca including non-Standard formats
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Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable
IV VD4-LVDS |
512 MByte
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LVDS |
Dual-LVDS |
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable
IV VD4-PoCL |
512 MByte
|
Camera Link 2.0 |
CL-base, -dual , -medium, -full, -deca including non-Standard formats
|
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
microEnable
IV VD4-PoCL (LVTTL) |
512 MByte
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Camera Link 2.0 |
CL-base, -dual , -medium, -full, -deca including non-Standard formats
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Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
PoCL SafePower |
microEnable
IV VQ4-GE
|
512 MByte
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GigE Vision
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Single Link, LAG (specific protocol)
|
Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
n/a |
microEnable
IV VQ4-GPoE
|
512 MByte
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GigE Vision
|
Single Link, LAG (specific protocol)
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Trigger/GPIO-IF (Opto Trigger, TTL Trigger) |
Power over Ethernet |
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