NBILink, GMIILink and MixedLink – Cabling
Cabling is an expensive portion of a machine vision system and HSLink offers scalable bandwidths to keep the cabling costs and size appropriate to the needs of the camera, whether the camera is of high bandwidth or low bandwidth.

Three formats exist in HSLink: NBILink, GMIILink and MixedLink. Each format contains a Control Channel, and one to seven video lane channels. The control channel is comprised of one downlink communication channel (Camera to Framegrabber) and one uplink communication channel Framegrabber to Camera), each of which are capable of carrying 300MB/s of information. The Control Channel is reserved to carry information regarding Trigger, GPIO, Ack/Nack, Command and Idle messages.

Each video lane has a bandwidth of 300MB/s for carrying image data. As the number of video lanes increases the bandwidth increases proportionally in 300MB/s steps. For simplicity, we’ll refer to these steps as x1 (300MB/s – one video lane) to x7 (2100MB/s – seven video lanes). Solutions beyond x7 are currently open for discussion and are not considered part of this primer.

To minimize cabling hardware, where appropriate the downlink communication channel of the Control Channel includes video along with Trigger, GPIO, Ack/Nack, Command and Idle Messages. To better understand the differences between NBILink, GMIILink and MixedLink, we’ll start with the GMIILink.

GMIILink uses off-the-shelf, multi-sourced, CX4 cable which provides eight differential pairs for use. Two of these differential pairs are used for the Control Channel. A minimum of three differential pairs have been defined as video lanes. This number can increase to six by using up all eight differential pairs in the CX4 cable. Thus, the GMIILink covers bandwidths from 3x to 6x.

The NBILink represents the lowest bandwidth options of x1 and x2, and thus requires the lowest cost cabling. To minimize cable needs, the NBILink combines video with the downlink Control Channel. Thus, only two physical connections are required in the cable hardware. At time of print, the connector/media for NBILink is under review, but for the x1 version both coax (RG59 x2) and Infiniband (IBx1) cables are options.

In either case, these cables can carry power thereby enabling a single compact cable solution for ever-shrinking cameras and micro-camera heads. For the x2 version two Infiniband cables are proposed or three coax.

Like NBILink, the MixedLink optimizes cable hardware by combining video with the downlink communications channel of the Control Channel. Thus, MixedLink provides a x7 solution on the same CX4 cable as GMIILink.

The current proposal is to run HSLink at a fixed 3.125 Gbps, thus ensure you purchase CX4 cables capable of handling this speed. The 3.125Gbps balances cost, throughput, transmission distance, power and simplifies the network discovery process.

The PHY (Serdes)
HSLink uses Serdes IC chips (The PHY) that are widely available from multiple vendors. The Serdes chips serialize and deserialize the information sent between cameras and framegrabbers using proven 8b/10b encoding technology. To reduce IC chip count, the Serdes function can be incorporated into the latest mid tier/low end FPGAs without the need for external devices, enabling extremely small camera implementations.

Also, IC and FPGA vendors continue to invest in 8b/10b technology, improving serial bit rates and power consumption for the foreseeable future. The HSLink protocol has been designed to take advantage of the upcoming improvements in Serdes technology. The Serdes IC chip is capable of handling both NBI and GMII protocols simultaneously for information exchange with the HSLink IP Core.

8b/10b encoding introduction
HSLink is built on proven 8b/10b data encoding technology. This encoding technology is the foundation of protocols known as PCIe, Gigabit Ethernet, 10-GigE, Infiniband, Fibre Channel, Serial Rapid I/O, CPRI and others.

These protocols span the computer and telecommunication industries and enjoy large economies of scale and the associated large investments from IC vendors to improve the physical layer. HSLink is a protocol designed to meet the unique real time, extreme bandwidth range, and data reliability requirements of machine vision. As HSLink is designed for machine vision, no extra overheads are incurred and unique features of the protocol reduce the vision system design costs.

8b/10b is a method that converts 8 data bits into 10 bits that are transmitted serially. Of the 1024 patterns that are available, 256 are defined data patterns and an additional 12 patterns are defined as control words or Kcodes. These patterns have a +/- image known as the disparity. Essentially the disparity signifies if the pattern has 6 or 4 '1' bits in the 10 bit pattern. The motivation for adding the extra 2 bits for transmission is that it enables:
1 DC balance, which makes data recovery easier after long transmission lines.
2 Clock Recovery, ensures there are sufficient edges in the serial stream to enable the receiver to find the data clock and recover the serial bits that were sent.
3 Kcodes are unique patterns that enable the receiver to find the byte boundaries or other low level tasks. Most physical layer devices (phy) use the pattern known as K28.5 as the byte alignment pattern. Kcodes are also used at the protocol level to signal events like start of message, end of message.
4 The encoding/decoding method uses two, small look-up tables and is very cost-effective.

Priority Technology
The priority level of the message types is defined by the HSLink interface requirements and implemented by the HSLink packet engine arbitrator technology.

HSLink uses a priority interrupt and continue packetization technology that maximizes the transmission bandwidth. The first-level priority technology achieves triggering jitter of 3.2ns and the second -level priority, GPIO messaging, achieves an uncertainty ranging from 3.2ns to 300ns depending on the trigger mode and other occurring activity. This 2nd level priority performance level is far superior to any available protocol today and will continue to out-perform any generic computer based protocols since this level of performance is not needed by those industries. HSLink is designed to meet the high speed line scan trigger needs and high speed area trigger needs of tomorrow, today. The triggering and real time control capability make HSLink unique and will continue to be an advantage it brings into the future. Micro head cameras are possible with this technology as no extra trigger circuitry/connector is required in the cameras.

HSLink is designed for a simple network, where it would be possible to install an I/O box and achieve real time control of peripheral devices from the frame grabber, or camera, such as LED strobes or air jets.

Data and Trigger Reliability
HSLink is targeted at critical customer product inspections where data errors can’t be tolerated. To meet this need, the protocol has been designed to tolerate single bit error events at the rate of 10-12, a typical specification for a PHY device. HSLink uses different methods to achieve reliability based on message type. The real time messages must be delivered without error the first time; there is no time to do a resend. The Trigger, GPIO, Ack/Nack are only a few bytes long and use 2 of 3 vote logic to overcome single bit errors. That is to say, all the bytes in the message are sent 3 times and the receiver considers the message to be received correctly when 2 of the 3 bytes are in agreement. The longer command and video messages use a CRC and data resend methodology to achieve data reliability.

A key feature for HSLink, which again enables low cost, small size, low power and simpler camera designs, when compared to software based protocols, is the hardware initiated video resend request. The real time error detection and request limits the amount of memory needed in the camera to successfully service a data resend request. Modern FPGAs easily accommodate the 4 rows of memory and the dual port feature of the memories simplifies the design of the resend memory controller.

CRC Calculation
The HSLink protocol is designed to support 1x to 20x or more data lanes real time. Traditional computer methods would require that the data be sent as one packet across all the lanes, i.e. a really wide and fast pipe. However, HSLink simplifies the approach and recognizes the limitations of FPGA implementation by calculating the CRC on a per lane basis, reducing the CRC calculation bandwidth to the 1x bandwidth
of 312.5 Mhz which is easily achievable in the lowest speed grade of StratixII™, Virtex5™, or the highest speed grade of the Cyclone 3™.

Newer generation FPGAs should be equally capable. Again HSLink simplifies implementation of band-width migration for the machine vision industry over the alternate approaches.

HSLink – Protocol
Two basic protocols are used within HSLink to address the wide range of camera and image processing needs in the machine vision industry, and to enable implementation with existing hardware today.

The first protocol is called the NBI protocol and defines the protocol used in the Control Channel. It also handles video in low bandwidth implementations, such as NBILink, and in MixedLink. The Control Channel, which uses NBI protocol, is common amongst all three Link types: NBILink, GMIILink and MixedLink.

The second protocol is called the GMII protocol and is used on the GMIILink configuration of the CX4 connector. This variant is designed to support low cost image processing through the data forwarding capability to 5 slave framegrabbers. Additionally, the Control Channel of the GMIILink provides a Bi-directional 300MB/s communication channel between slaves and the master framegrabber.
The Mixed protocol adds video information to the control channel of the GMIILink variant to maximize the video bandwidth on the single cable.

NBI (Nine Bit Interface) Protocol Overview
This protocol provides the command and low jitter trigger capability found in all HSLink variants. In lower bandwidth configurations this channel also carries video data. It derives its name from the interface to the physical layer device (PHY). The nine bits consist of 8 bit data and a K-code flag. The protocol has complete control over the K-codes and as such has designated specific Kcodes to start specific message types.

A key requirement for this channel to operate is that the camera must frequency lock to the frame grabber clock thereby enabling the low jitter trigger to be transferred from one end of the cable to the other end. This technique is used in the CPRI protocol found in cell phone base stations and enables the frame-grabber FPGA to receive data from many cameras without the concern for the limited number of FPGA clock nets.

GMII (Gigabit Media Independent Interface) Protocol Overview
The GMII protocol defined in HSLink is based on the GMII protocol foundation that was developed for GigE applications. It defines the start kcode, stop kcodes and the idle sequence that is implemented by the phy.

The HSLink GMII protocol defines the number of preamble bytes, the header, the video data format, the CRC and the minimum number of idle bytes to support data forwarding to 5 slave framegrabbers. This data forwarding is possible because GigE is designed to support small frequency variations at each end of the cable, and therefore the off the shelf phys include rate matching fifos. Additionally most off-the-shelf phys are able to loop the data that was received to the transmitter. These two features are used to advantage in the GMIILink as the cable bandwidth is asymmetric and the unused transmitters in the frame-grabber are put to use by forwarding the data to a connector connected with a slave frame grabber.

Trigger Packet
Real time triggering is key to a successful machine vision link. HSLink achieves 3.2ns of jitter from one end of the cable to the other with today’s technology. This level of performance is sufficient for the next 5
to 10 years and it is possible that FPGA fabrics will be able to run at 625 MHz in the future, thereby improving (reducing) the jitter without any change to the protocol.

HSLink triggering is built upon the concepts used in Camera Link but extends Camera Link and offers 8 standard triggering modes. This triggering flexibility ensures that camera needs are met now and into the future and standardized trigger definition enables ease of end customer use.

GMII Video Packet
Similar to the NBI Video Packet, the GMII video data is "pushed" into the frame grabber. The data presentation on the link is well defined in order to reduce the complexity of data reorganization and simplify frame grabber design and power on discovery process.

The GMII video packet is used to send video data from the camera to the framegrabber over dedicated video data lanes. The GMII start and stop Kcodes are inserted by the phy. The 16 preamble and minimum 16 idle bytes are defined by HSLink to support up to 5 slaves. The machine-vision-specific header is added after the preamble and uses a redundant data technique to ensure that the header is received correctly. CRC is used to detect errors in the data. The HSLink IP Core requests a data resend
should an error in either the header or data be found.

Command Packet
The command packet has 4th level priority. It is used to send information to the camera/frame grabber like the serial link in Camera Link.

As the protocol is designed to support intermediate devices between the camera and frame grabber, there is the need to include a target address. The network architecture supported by HSLink is very simple in order to keep the addressing overheads small and the software support for the network easy to implement. Also, HSLink supports the camera initiating a communication with the framegrabber.