Camera Link HS: the best interface for demanding applications
Leveraging the key strengths
of Camera Link to define the camera communication interface of the future
The interface that helps your application
run faster and with fewer errors
from the standpoint that a cameras is only as good as its connecting cable,
a group of members from the Automated Imaging Association
(AIA) has worked to overcome the speed limitations of the current Camera
Link interface for line scan cameras.
Growing machine-vision needs wanting higher resolution and faster frame
rates have placed a increased demand on bandwidth and the selected committee
members of the AIA have worked to develop the next generation protocol
standard to address, specifically, these increased needs. The concept
is hosted by AIA and is
being developed as a global standard where developmental priorities include:
designing the interface from a system point-of-view, keeping a cap on
costs while maintaining ease-of-use, flexibility and data reliability
essential for robust use by customers and also attempting to eliminate
the large number of cables needed for fast transfer speeds in multi-camera
While carrying the Camera Link name and having a feature set that is
very close to its namesake, the CLHS standard is a new type of
interface sharing the same message types as the Camera Link protocols
but differing in implementation and how messages are carried from one
end of the cable to the other.
The best interface for demanding applications
According to Mike Meithig, committee chair and technical manager for Teledyne
Dalsa, the challenge was to reduce wire count by putting video, communication,
high-speed trigger and GPIO on a single wire. Meithig also explained that
the committee needed to create a standard that offered greater reliability
by eliminating the bit errors sometimes associated with Camera Link technology.
"In Camera Link HS there are redundant trigger codes as well
as video hardware resend to guarantee 100% reliable data," said
Meithig, "The Camera Link HS SerDes can
be implemented inside an FPGA with external equalizer
ships from multiple suppliers and 100% reliable data is achieved with
memory sizes that are small enough to be implemented inside the FPGA to
reduce costs, size and power."
Supporting both multi-camera and multi-frame grabber systems and with
protocols designed for a 10Gbps SerDes (downwardly scalable, if necessary)
the new interface prioritizes messages and maintains the real-time low-latency
and low jitter of Camera Link and so eliminating the need for a separate
Bob McCurrach, AIA's Director of Standards Development, said: "Camera
LInk HS is truly a real-time connection, there are no latency issues.
Because Camera Link is so well known and widely used, we're sure to see
CAmera Link HS products muliply in te next year."
and benefits of Camera Link HS
• Standard offering
the highest bandwidth
• Cost effective at lower bandwidths
• 32 GPIO with latencies of
100 to 300 ns in each cable direction
• Employs off the shelf technology
from multiple suppliers
• Designed to migrate to higher speed serdes
• 100% reliable transmission, even with transmission
• No need for a
separate trigger cable
• Camera size is minimized.
• Power over Camera Link HS
GeniCam compliant for easy transition from CL to CLHS
• 300 metres fibre optic cable
• Camera Link HS protocol - exceeding
95% video efficiency
• Serial protocol. lowest
trigger latency and lowest jitter: 100ns +/-1.6ns jitter
Miethig, Chair of the AIA Camera Link HS Standard Committee, explains
the features and benefits of the new CLHS interface
Automated Imaging Association
AIA is the world's largest machine vision trade group comprising more
than 300 members from 30 countries. Membership comprising representatives
from various machine vision arenas and include system integrators, camera,
lighting, vision software providers, researchers, manufacturers and distributors.
Members of the subcommittee for research into CLHS include camera, frame
grabber and cable companies working on the specification together.
An integrated circuit transmitter/receiver that converts parallel data
to serial data and vice versa. Commonly used in high-speed communications.
Field-programmable gate array
An FPGA is an integrated circuit designed to be configured by the customer
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