PC - LineScan
Back to Digital Frame Grabbers
Back to Coreco Frame Grabbers

PC-LineScan is a high performance PCI-bus frame grabber that provides onboard acceleration for high-speed vision tasks utilizing digital cameras. Designed for challenging line scan applications, PC-LineScan includes performance enhancements that collect and analyze large amounts of data in real-time and compensates for variations in lighting. PC-LineScan integrates the real-time processing functions needed for high-speed line inspection applications directly on the board itself. This off-loads the host CPU and provides users with increased speed and bandwidth to handle other tasks, such as motion control.

PC-LineScan is based on an expandable architecture that supports real-time processing functions that works to accelerate machine vision tasks. This new design has been fine-tuned for line scan applications. Features that were traditionally handled more slowly by software are now available onboard in real-time, including Run-Length Encoding and Flat-Field Correction. PC-LineScan also supports a plug-in expansion module that can be custom designed to meet specific application needs.

Accompanying the new features of the PC-LineScan are several performance enhancements. The 32-bit differential camera data interface now operates at frequencies up to 62.5MHz. This provides for continuous image acquisition at an incredible 250MB/sec. Another enhancement to PC-LineScan is a larger 32MB SDRAM-based image buffer. Finally, the PC-LineScan supports a plug-in daughter module to support additional real-time processing functions.

Key features

• 120MB/sec bus master transfer to host that guarantees no missing lines and a low host CPU burden
• On-the-fly re-sequencing of image data for multi-tap cameras
• Run Length Encoding gathers/compresses common data minimizing transfer time
• Flat-Field Correction compensates for lighting nonuniformities
• OPTO- 22 compatible parallel I/O (8/8) port eliminates need for an additional I/O card
• Dual 16 x 16 LUT for image transformations
• 32 MB SDRAM image buffer supports acquisition rates up 250MB/sec (32 bits @ 62.5 MHz)
• Scatter gather feature for high memory-efficient image transfers and management

Video Formats

• 32-bit differential LVDS input up to 62.5 MHz or RS-422 input up to 25 MHz pixel acquisition rates
• Supports single-tap, dual-tap, or quad-tap monochrome or color digital cameras

Camera Data Inputs
• 32-bit LVDS (EIA-644) or RS-422 camera data interface at up to 62.5MHz (25MHz for RS-422). Compatible with 8-bit (single, dual, quad tap), 16-bit (single, dual) and 32-bit (single) digital line-scan and area-scan cameras. Also supports 10/12/14-bit image data (single or dual tap) and 8-bit color cameras
• Multiple camera support: up to three 8-bit cameras, up to two 10-bit, 12-bit, 14-bit, or 16-bit cameras, and one 24-bit or 32-bit camera. There is one set of timing inputs; cameras must be externally synchronized
• Multiple boards can be synchronized for a wider multi-tap data width or more multi-camera support

Camera Timing Inputs
• RS-422 or EIA-644 LVDS data and timing inputs

Differential timing inputs
• HDrive or Line Enable (LEN),VDrive or Frame Enable (FEN), and a Multipurpose input (MULTI) for field, etc.

Programmable signal polarities
• Pixel Clock Input (PCLK): differential, programmable polarity edge sampling, RS-422 0-25 MHz, and LVDS 0-62.5 MHz
• Line-scan and area-scan modes

External Trigger Inputs
• Two independent programmable triggers provide additional flexibility: start and stop, sync and trigger, divide and trigger
• Programmable polarity - rising or falling edge triggered
• Software selectable sources for each trigger: software trigger, TTL input, opto-coupled input, or differential input (same signaling as data/timing, LVDS, or RS-422)
• Glitch detector/filter to condition noisy trigger sources
• The trigger rate-divider circuit supports acquisition at a user-selectable division of the incoming trigger rate

Camera Timing Outputs
• The RS-422 or LVDS (EIA-644) are the same as data and timing inputs
• Output signals: Pixel Clock (CCLK), Camera External Synchronization (EXSYNC), and Programmable Integration or Exposure Control (PRI)
• Deterministic multi-camera timing. EXSYNC and PRI can be synchronized to rising or falling edge of CCLK
• Up to three identical sets of timing outputs controls up to three cameras. Two dedicated sets of outputs. A third set may be enabled on the camera control outputs
• Clock Output (CCLK): differential programmable frequency 320 KHz to 100 MHz. Maximum frequency may be limited by signaling standard, cable quality, and length
• External Sync Output (EXSYNC): differential programmable polarity, programmable period 210 ns to 18.75 s. User-programmable characteristics (i.e., pulse width, pulse delay, etc.)
• Programmable Integration Output (PRI): differential programmable polarity. User-programmable characteristics (i.e., start-point, stop-point, pulse width, pulse delay, etc).

Camera Control Outputs
• Four logic outputs to control camera modes: the RS-422 or LVDS (EIA-644) are the same as data and timing inputs
• Three outputs can be switched (by software) to timing output to support a third camera

Flat-Field Correction
• Compensates for lighting nonuniformities (shading) and imager nonuniformities via real-time pixel-by-pixel gain/offset corrections
• Corrects line-scan images up to 64K pixels/line
• Works with 8/10/12-bit image data
• Linear correction algorithm: y(DN) = x*{n(DN)-a}. DN = digital number; n(DN) = raw data; a = dark offset (imager fixed pattern noise); x = correction factor; y(DN) = corrected data
• 8-Bit data: n(DN) = 0-255 (8 bits); a = 0-63 (6 bits, 25% of full scale value); x = 0-3.996 (2 integer bits, 8 fractional bits); y(DN) = 0-255 (results are rounded to 8-bits)
• 10-Bit data: n(DN) = 0-1023 (10 bits); a = 0-1023 (10 bits, 100% of full scale value); x = 0-3.9998 (2 integer bits, 12 fractional bits); y(DN) = 0-1023 (results are rounded to 10 bits)
• 12-Bit data: n(DN) = 0-4095 (12 bits); a = 0-1023 (10 bits, 25% of full scale value); x = 0-3.9998 (2 integer bits, 12 fractional bits); y(DN) = 0-4095 (results are rounded to 12-bits)
• Operates at maximum data rates
• Processes up to 4 channels simultaneously for multi-tap camera applications

Input Look-Up Tables
• Two 16 by 16 Look-up Tables (LUT) can be programmed and used as four 8 by 8
• Perform point transformation before acquisition into image memory: threshold, invert, absolute value, contrast adjustment, binarization
• Perform simple math based on 8-bit data input and constant, or based on two 8-bit data inputs: add, subtract, average, and multiply
• Normalizes 10, 12, 14-bit data to 16-bits

Run-Length Encoding
• Real-time "streak" feature extraction for line-scan applications
• Supports simultaneous RLE processing AND storage of the original image into the image buffer
• RLE results is 0.5MB and may be stored in either the Feature RAMs or the image buffer
• High-speed bus master transfers of data results from Feature RAMs to the host
• Feature RAMs support simultaneous RLE processing and access to data results by the host
• 7-bit "Tags" allow up to 128 different features to be monitored

• Gray Scale Thresholding
• Edge Detection and Gauging
• Other line-based processing algorithms
• Significantly reduces image data volume
• Processes both single-tap and multi-tap image data
• Operates at maximum data rates

Expansion Slot
• Supports a plug-in daughter module for real-time processing functions
• Functionally located between the pixel LUTs and the image buffer
• Full 32-bit image data pipeline
• Can function in parallel with the built-in RLE circuit
• Daughter card results may be transferred directly to the host or stored in the image buffer
• High-speed bus master transfer of data results to the host is supported

Multi-Tap Image Resequencing
• Resequences multi-tap camera data in real-time: 2 tap, 4 tap, odd/even pixel, odd/even line, opposite scan, multiple quadrant, etc.
• No host CPU intervention required (0 overhead)

Image Buffer Memory
• 32MB linear mapped SDRAM
• Acquires at camera data rate (up to 100MB/sec for RS-422 or 250MB/sec for LVDS), transfers to host at PCI-bus data rate (up to 132MB/sec theoretical maximum)
• Color image data can be stored as 32-bit zero-filled or 24-bit packed format
• Programmable decimation by 2, 4, 8, 16; independent horizontal and vertical; performed during acquisition, affects acquired image data
• Programmable "valid video window" timing - 1 to 64K pixels per line, 1 to 64K lines per frame

Output Scatter Gather Table
• "DMA Table" performs "destination scatter gather" for bus master transfer from image memory to PCI-bus host

Bus Master Image Transfers
• Transfer rates up to 132MB/sec theoretical limit of PCI-bus, limited by bus traffic, block size, and capability of destination device
• Bus master transfer to PCI-bus host memory, VGA, or other PCI-bus system resources
• Hardware "scatter gather" table provides efficient automated transfer
• Optional clipping during bus master transfer to VGA memory removes "color dots" in Windows (Windows reserved colors)
• Optional padding 8-bit to 16-bit data during bus master transfer to VGA secondary surface, for 4:2:2 display; also 16-bit to 16-bit padding shifts, 16-bit monochrome to 8-bit adds neutral CrCb value
• Supports basic image transforms: flip, mirror, rotate by 180
• Supports "planar" 8-bit transfer of 24-bit color data during bus master transfer

Parallel I/O Port
• One 16-bit parallel I/O port: 8-bit TTL input, 8-bit TTL/CMOS output
• Strobe input for latching input data, programmable rising or falling edge
• Strobe output for latching output data
• 50-pin header is pin-compatible with OPTO-22 module racks

Serial I/O Ports
• Two RS-232D serial ports on two 10-pin headers
• Software and register compatible with 16450 and 16550 devices
• l TXD, RXD, CTS, RTS on each port
• Data rates from 50 to 128K baud

Environmental
• Board Size - 312.0 by 106.8 mm; 12.283 by 4.205 inches (Full Card)
• Operating Temperature - 10-60 degrees Celsius
• Relative Humidity - 0-90% non-condensing
• Power Requirements (estimated) - 2.5 Amperes at +5 volts, 5 volt to 3.3 volt conversion performed on the PC-Linescan

Sensor Interface
• Input - 2 RGB color or up to 2 sets of 3 synchronous RS-170 CCIR monochrome cameras
• Programmable time base generator for standard and nonstandard video formats. Resolution to 4K x 4K
• PLL or XTAL mode (Outputs horizontal/composite, vertical and reset timing to camera. 3 sync sets available for driving 3 simultaneous mono cameras)
• Progressive scan (noninterlaced) signal supported
• Variable scan cameras are supported, single ended TTL timing (0 - 30 MHz)
• Dual-tap cameras are supported using two of the three RGB channels

Video Digitizer
• Monotonic 24-bit flash ADC; Input sample rate programmable to 30 MHz, 12Mhz video bandwidth, 48DB SNR

Video Memory
• 4MB

Video Signal Conditioning
• Programmable input gain selection (4 gain factors)
• Programmable positive and negative signal reference: 0 to +5 Volts in 256 steps
• Video low pass anti-aliasing filter
• DC restoration: programmable clamp pulse

On Board Digital I/O
• OPTO-22 compatible

Color Space Converter and Look-Up-Table
• 10-bit precision 3x3 30 MHz matrix multiplier and a 64KDWORD (32 in - 32 out) ILUT following ADC

Transfer Rates
• Less than 4 ms per image (Requires a motherboard with burst mode to host memory)
• Contact Coreco Imaging for suggested motherboards

External Trigger, Strobe Control, and Frame Reset
• Trigger provides synchronization to external events: 3 TTL with Schmitt Trigger and (2) Opto-coupled, (1) RS-422 differential
• Flexible strobe control
• Support for frame reset cameras
• Edonpisha supported

Video Window Generator
• Programmable resolutions up to 4k x 4k. Area of Interest (AOI)

Interrupts
• Software interrupts can be generated at the start of the strobe pulse, the start of a vertical blank, or at the end of a trigger cycle

Hardware Color Dot Clipping

On Board Decimation

Data formatting
• 8-bit Red, Green, or Blue
• 16-bit (converts 24-bit RGB to 16-bit YcrCb 4:2:2)
• 24-bit (packs 24-bit RGB to data into 32-bit DWORDS). This saves memory and supports standard color VGA cards
• 32-bit standard RGBa or aRGB format
• 32-bit planar mode separates data from each 8-bit input into its own plane in memory.

Display - Windows
• Display resolution as per installed VGA device driver
• A DirectX compatible SVGA adapter required for real-time display

Automatic Double Buffered Full Frame Acquisition

Bus Requirements
• 32-bit PCI slot
• 1.3 Amps @ +5 volts
• 0.2 Amps @ + 12 volts
• 8" long PCI card

Power Output
• 500 ma @ +12 volts per camera (1 Amp total)